Today's mobile systems-on-chip (SoCs) include multiple subsystems, e.g., Apps CPU, GPU, and Video, that share a common main memory based on DRAM technology. Each of the subsystems employs one or more local memories for fast access to frequently used data and to minimize accesses to main memory. The local memories are typically configured as caches that are either software managed or hardware managed depending on the subsystem needs. Performance scaling across product generations requires increasing the size of the local memories. This scaling strategy suffers the drawback of increased area and static power. Also, in a majority of the use cases, the utilization of the local memories can be low since all of the subsystems are not simultaneously active.
A shared system cache can address these drawbacks by pooling all of the local memories into a shared on-chip memory resource. The system cache can potentially save area since its size is expected to be smaller than the aggregate size of all the local memories. The system cache is also expected to provide significant power savings and higher performance in the common use cases of one or two active subsystems. For these use scenarios, the active subsystems will have access to a potentially bigger on-chip local memory that can reduce the number of accesses to main memory and result in higher overall performance and lower power.
In a system in which a shared cache is available for SoC subsystems, a portion of the system cache is partitioned to be used exclusively for use by an assigned SoC master. There are several issues that arise in such systems. The master could be power collapsed at system runtime. In current systems the application processor subsystem (APSS) manages the entire shared cache. If the APSS is power collapsed, other masters are not able to execute cache management commands, such as deactivating or flushing a cache partition. Managing the system cache through the APSS also creates greater overhead using extra software interaction when managing the system cache.